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Chapter 24: Boards Library
24–7
Board Configuration
Stratix III EP3SL150 DSP Board
The Stratix III EP3SL150 DSP board provides a hardware platform for developing and
prototyping low-power, high-volume, feature-rich designs that demonstrate the
Stratix III device’s on-chip memory, embedded multipliers, and the Nios ? II
embedded soft processor.
Table 24–3 lists the blocks available to support the Stratix III EP3SL150 DSP board.
Table 24–3. Stratix III EP3SL150 DSP Board Blocks
Block
Display0
A2D_1_HSMC_A,
A2D_1_HSMC_B,
A2D_2_HSMC_A,
A2D_2_HSMC_B
D2A_1_HSMC_A,
D2A_1_HSMC_B,
D2A_2_HSMC_A,
D2A_2_HSMC_B
Dip Switch
LED0–LED7
PB0–PB3,
CPU_RESETN
Description
User defined 4-digit seven-segment LED display (U27).
Controls 14-bit signed analog-to-digital converters on the optional high speed
mezzanine cards (HSMC). You can optionally specify the clock signal.
Controls the 14-bit unsigned digital-to-analog converters on the optional high speed
mezzanine cards (HSMC).
Controls the user-definable dual in-line package switch (SW5). You can optionally
specify the clock signal.
Controls eight user-definable LEDs (D20–D27).
Controls four user-definable push-button switches (S2–S5) and the CPU reset
push-button (S6). You can optionally specify the clock signal.
f For information about setting up the board and the supported hardware features,
refer to the Stratix III Development Board, Reference Manual .
Altera provides the following design examples for the Stratix III EP3SL150 DSP board:
■
■
■
■
Test3S150Board_Leds.mdl : tests the LEDs and push-button switches on the main
development board.
Test3S150Board_QuadDisplay.mdl : tests the 7-segment display on the main
development board.
Test3S150Board_HSMA.mdl : tests the analog-to-digital and digital-to-analog
converters on the daughtercard connected to HSMC port A.
Test3S150Board_HSMB.mdl : tests the analog-to-digital and digital-to-analog
converters on the daughtercard connected to HSMC port B.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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